From da3ef0f81250b5a680001610028ff35ee94741bc Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Tue, 7 May 2013 16:23:31 +0200 Subject: [PATCH] AMD IOMMU: fill msi_desc fields required by commit fe017c59 Since the AMD IOMMU code relies on the x86 generic MSI code, it also needs to be updated to match "x86/MSI: cleanup to prepare for multi- vector MSI". Signed-off-by: Jan Beulich Acked-by: Suravee Suthikulanit --- xen/drivers/passthrough/amd/iommu_init.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/xen/drivers/passthrough/amd/iommu_init.c b/xen/drivers/passthrough/amd/iommu_init.c index 73d9ce4666..abb94ece54 100644 --- a/xen/drivers/passthrough/amd/iommu_init.c +++ b/xen/drivers/passthrough/amd/iommu_init.c @@ -775,9 +775,16 @@ static bool_t __init set_iommu_interrupt_handler(struct amd_iommu *iommu) control = pci_conf_read16(iommu->seg, PCI_BUS(iommu->bdf), PCI_SLOT(iommu->bdf), PCI_FUNC(iommu->bdf), iommu->msi.msi_attrib.pos + PCI_MSI_FLAGS); - iommu->msi.msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); - desc->handler = control & PCI_MSI_FLAGS_MASKBIT ? - &iommu_maskable_msi_type : &iommu_msi_type; + iommu->msi.msi.nvec = 1; + if ( is_mask_bit_support(control) ) + { + iommu->msi.msi_attrib.maskbit = 1; + iommu->msi.msi.mpos = msi_mask_bits_reg(iommu->msi.msi_attrib.pos, + is_64bit_address(control)); + desc->handler = &iommu_maskable_msi_type; + } + else + desc->handler = &iommu_msi_type; ret = request_irq(irq, iommu_interrupt_handler, 0, "amd_iommu", iommu); if ( ret ) { -- 2.30.2